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| 74VHC32 Quad 2-Input OR Gate November 1992 Revised February 2005 74VHC32 Quad 2-Input OR Gate General Description The VHC32 is an advanced high speed CMOS 2-Input OR Gate fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD ICC 3.8 ns (typ) at VCC 2 PA (Max) at TA 5V 25qC VNIL 28% VCC (Min) s Low Power Dissipation: s High Noise Immunity: VNIH s Low Noise: VOLP s Power down protection is provided on all inputs 0.8V (Max) s Pin and Function Compatible with 74HC32 Ordering Code: Order Number 74VHC32M 74VHC32MX_NL (Note 1) 74VHC32SJ 74VHC32MTC 74VHC32MTCX_NL (Note 1) 74VHC32N Package Number M14A M14A M14D MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol IEEE/IEC Connection Diagram Truth Table Pin Descriptions Pin Names An, Bn On Description Inputs Outputs DS011518 A H L H L B H H L L O H H H L (c) 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC32 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Recommended Operating Conditions (Note 3) Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r0.3V 5.0V r0.5V 0 a 100 ns/V 0 a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC 40qC to 85qC Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 5.5 2.0 3.0 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 5.5 2.0 20.0 0 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VIN 4 mA 8 mA V V VIN IOH IOH VIH IOL or VIL V 25qC Typ Max TA 40qC to 85qC Max Min 1.50 0.7 VCC Units V Conditions 0.50 0.3 VCC V VIN VIH IOH or VIL 50 PA 4 mA 8 mA 50 PA r0.1 r1.0 PA PA 5.5V or GND VCC or GND Noise Characteristics Symbol VOLP (Note 4) VOLV (Note 4) VIHD (Note 4) VILD (Note 4) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF 5.0 3.5 V CL 50 pF 5.0 VCC (V) 5.0 TA Typ 0.3 25qC Limit 0.8 V V CL CL 50 pF 50 pF Units Conditions 0.3 0.8 Note 4: Parameter guaranteed by design. www.fairchildsemi.com 2 74VHC32 AC Electrical Characteristics Symbol tPHL tPLH Parameter Propagation Delay VCC (V) 3.3 TA Min 25qC Typ 5.5 8.0 3.8 5.3 4 14 Max 7.9 11.4 5.5 7.5 10 TA 40qC to 85qC Max 9.5 13.0 6.5 8.5 10 1.0 1.0 1.0 1.0 Min Units ns ns pF pF CL CL CL CL VCC Conditions 15 pF 50 pF 15 pF 50 pF Open r0.3 5.0 r0.5 CIN CPD Input Capacitance Power Dissipation Capacitance (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN I CC/4 (per gate). 3 www.fairchildsemi.com 74VHC32 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 74VHC32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74VHC32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 74VHC32 Quad 2-Input OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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